Parts Average Testing ( PAT ) has recently been adopted by a number of semiconductor companies, primarily to help them meet the stringent requirements of the automotive industry (Automotive Electronics Council: AEC-Q001-Rev C). Indeed, reliability studies have shown that semiconductor parts that have abnormal characteristics tend to be higher contributors to long-term quality and reliability problems. That is, devices that originally passed all manufacturing tests but could be considered "outliers" compared to other parts in the same population or lot, are more likely to fail in the field. This is the basis for the process known as Parts Average Testing ( PAT ), which proactively identifies these outliers for exclusion from production shipments. This is done by modifying the pass/fail test limits based on statistical sampling of multiple devices.

Parts Average Testing ( PAT ) as detailed into the Automotive Electronics Council AEC-Q001-Rev C specifications only covers DPM techniques for normal (Gaussian) distributions. However, many distributions do not fall into the Gaussian category and require adapted PAT outlier detection methods to avoid excessive yield loss, or incorrect outlier detection.

Using outlier identification/removal techniques allow to:

  • Significantly reduce quality and reliability issues and their consequences (e.g. customer returns, product recalls)

  • Quickly identify process shifts. 

  • Provide a means to communicate rapid feedback amongst the members of the supply chain

  • Improve reliability of products and processes

One of the major issues cost-conscious suppliers face is how to make the trade-off between lower defects per million (DPM) and yield. That was a key design consideration for the Galaxy PAT-Man™ product: a closed-loop, optimized solution for managing the entire DPM reduction process.

Galaxy's PAT-Man™ is a comprehensive solution for PAT and related DPM reduction techniques, which manages the DPM reduction process from initial wafer lot characterization to final-test yield monitoring. Based on a proven architecture and intuitive user interface, PAT-Man™ integrates easily with your existing production test environment and provides the fastest and most cost-effective solution for DPM reduction in the industry.

 

Typical PAT-Man™ Applications:

  • Wafer sort : Post-processing step that covers parametric PAT, geographic PAT (good die in bad neighborhood), reticle PAT, and combinations of the above.

  • Final Test : Real-time process on the tester, which covers parametric PAT, trend monitoring, yield monitoring and alarm/reporting notifications.

  • Static PAT limits : Support for Automotive Electronics Council AEC-Q001 Rev C and JEDEC specifications

  • Dynamic PAT limit: Auto-adaptive algorithms for Gaussian distributions as well as non-Gaussian for minimized yield loss.

Galaxy Semiconductor Inc. | 255 Constitution Dr. Menlo Park, CA 94025 USA | www.galaxysemi.com